PIC16(L)F1824/1828
TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELA
CCP1CON
CCP2CON
—
P1M1
P2M1
—
P1M0
P2M0
—
DC1B1
DC2B1
ANSA4
DC1B0
DC2B0
—
CCP1M3
CCP2M3
ANSA2
CCP1M2
CCP2M2
ANSA1
CCP1M1
CCP2M1
INLVLA
INTCON
PIE1
PIR1
TMR1H
TMR1L
TRISA
T1CON
T1GCON
Legend:
*
Note 1:
—
—
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
—
—
TRISA5 TRISA4
TRISA3
TRISA2 TRISA1
TMR1CS1 TMR1CS0
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL T1GSS1
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
PIC16F/LF1828 only.
Bit 0
ANSA0
CCP1M0
CCP2M0
INLVLA0
IOCIF
TMR1IE
TMR1IF
TRISA0
TMR1ON
T1GSS0
Register
on Page
127
238
238
128
93
94
97
193*
193*
126
197
198
2010 Microchip Technology Inc.
Preliminary
DS41419B-page 199