PIC16F1828T-I/SL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F1828T-I/SL
Microchip Technology
PIC16F1828T-I/SL Datasheet PDF : 419 Pages
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25.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSP1CON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.
TABLE 25-2: I2C BUS TERMS
TERM
Description
Transmitter
Receiver
Master
Slave
The device which shifts data out
onto the bus.
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
The device addressed by the mas-
ter.
Multi-master
A bus with more than one device
that can initiate data transfers.
Arbitration
Synchronization
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Addressed
Slave
Matching
Address
Any time one or more master
devices are controlling the bus.
Slave device that has received a
matching address and is actively
being clocked by a master.
Address byte that is clocked into a
slave that matches the value
stored in SSP1ADD.
Write Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
PIC16(L)F1824/1828
2010 Microchip Technology Inc.
Preliminary
DS41419B-page 257
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