PIC16(L)F1824/1828
FIGURE 26-4:
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1
Word 2
1 TCY
Start bit
Word 1
Transmit Shift Reg.
bit 0
1 TCY
bit 1
Word 1
bit 7/8 Stop bit
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON0 RXDTSEL SDOSEL(2) SSSEL(2)
—
T1GSEL TXCKSEL
—
—
BAUDCON ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INLVLA(3)
—
—
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
INLVLB(1)
INLVLB7 INLVLB6 INLVLB5 INLVLB4
—
—
—
—
INLVLC
INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
RCSTA
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
SPBRGL
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
SPBRGH
BRG15
BRG14
BRG13 BRG12 BRG11 BRG10
BRG9
BRG8
TRISA3)
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISB(1)
TRISB7
TRISB6 TRISB5 TRISB4
—
—
—
—
TRISC
TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
Legend:
*
Note 1:
2:
3:
— = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
PIC16F/LF1828 only.
PIC16F/LF1824 only.
Unshaded cells apply to PIC16F/LF1824 only.
Register on
Page
122
308
128
133
139
93
94
97
307
309*
309*
126
132
132
299*
306
2010 Microchip Technology Inc.
Preliminary
DS41419B-page 301