PIC16F1828T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1828T-I/SL

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16(L)F1824/1828

FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

pin

TX/CK pin

(SCKP = 0)

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

CREN bit ‘0’

‘0’

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

APFCON0

RXDTSEL SDOSEL(1) SSSEL(1)

—

T1GSEL TXCKSEL

—

—

BAUDCON

ABDOVF RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSP1IE CCP1IE TMR2IE TMR1IE

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF CCP1IF TMR2IF TMR1IF

RCREG

EUSART Receive Data Register

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

SPBRGL

BRG7

BRG6

BRG5

BRG4

BRG3

BRG2

BRG1

BRG0

SPBRGH

BRG15

BRG14 BRG13 BRG12 BRG11 BRG10

BRG9

BRG8

TXSTA

Legend:

*

Note 1:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

Page provides register information.

PIC16F/LF1824 only.

Register

on Page

122

308

93

94

97

302*

307

309*

309*

306

 2010 Microchip Technology Inc.

Preliminary

DS41419B-page 321

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