PIC16LF1828T-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1828T-I/ML

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16(L)F1824/1828

TABLE 30-15: I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min. Max. Units

Conditions

SP100*

SP101*

SP102*

SP103*

SP106*

SP107*

SP109*

SP110*

SP111

*

Note 1:

2:

THIGH Clock high time

100 kHz mode

4.0

—

s Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

s Device must operate at a

minimum of 10 MHz

SSPx module

1.5TCY

—

—

TLOW Clock low time

100 kHz mode

4.7

—

s Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

s Device must operate at a

minimum of 10 MHz

SSPx module

1.5TCY

—

—

TR

SDAx and SCLx 100 kHz mode

—

1000 ns

rise time

400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from

10-400 pF

TF

SDAx and SCLx fall 100 kHz mode

—

250 ns

time

400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from

10-400 pF

THD:DAT Data input hold time 100 kHz mode

0

—

ns

400 kHz mode

0

0.9 s

TSU:DAT Data input setup 100 kHz mode

250

—

ns (Note 2)

time

400 kHz mode

100

—

ns

TAA

Output valid from 100 kHz mode

clock

400 kHz mode

—

3500 ns (Note 1)

—

—

ns

TBUF

Bus free time

100 kHz mode

400 kHz mode

4.7

—

s Time the bus must be free

1.3

—

s before a new transmission

can start

CB

Bus capacitive loading

—

400 pF

These parameters are characterized but not tested.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.

A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-

nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according

to the Standard mode I2C bus specification), before the SCLx line is released.

 2010 Microchip Technology Inc.

Preliminary

DS41419B-page 381

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