PIC16F1938-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1938-I/SP

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP™ Technology

Microchip Technology 

PIC16F193X/LF193X

TABLE 28-17: I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min. Max. Units

Conditions

SP100* THIGH Clock high time

100 kHz mode

4.0

—

μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

μs Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY —

SP101* TLOW Clock low time

100 kHz mode

4.7

—

μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

μs Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY —

SP102* TR

SDA and SCL rise 100 kHz mode

—

1000

time

400 kHz mode 20 + 0.1CB 300

ns

ns CB is specified to be from

10-400 pF

SP103* TF

SDA and SCL fall 100 kHz mode

—

250

time

400 kHz mode 20 + 0.1CB 250

ns

ns CB is specified to be from

10-400 pF

SP90* TSU:STA Start condition

100 kHz mode

4.7

—

μs Only relevant for

setup time

400 kHz mode

0.6

—

μs Repeated Start condition

SP91* THD:STA Start condition hold 100 kHz mode

4.0

—

μs After this period the first

time

400 kHz mode

0.6

—

μs clock pulse is generated

SP106* THD:DAT Data input hold time 100 kHz mode

0

—

ns

400 kHz mode

0

0.9 μs

SP107* TSU:DAT Data input setup 100 kHz mode

250

—

ns (Note 2)

time

400 kHz mode

100

—

ns

SP92* TSU:STO Stop condition

100 kHz mode

4.7

—

μs

setup time

400 kHz mode

0.6

—

μs

SP109* TAA

Output valid from 100 kHz mode

clock

400 kHz mode

—

3500 ns (Note 1)

—

—

ns

SP110* TBUF

Bus free time

100 kHz mode

400 kHz mode

4.7

—

μs Time the bus must be free

1.3

—

μs before a new transmission

can start

SP111 CB

Bus capacitive loading

—

400 pF

* These parameters are characterized but not tested.

Note 1:

2:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,

it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to

the Standard mode I2C bus specification), before the SCL line is released.

DS41364B-page 386

Preliminary

© 2009 Microchip Technology Inc.

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