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PIC16F1936T-ESS View Datasheet(PDF) - Microchip Technology

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Description
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PIC16F1936T-ESS Datasheet PDF : 418 Pages
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PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 8
400h(2) INDF0
401h(2) INDF1
402h(2) PCL
403h(2) STATUS
404h(2) FSR0L
405h(2) FSR0H
406h(2) FSR1L
407h(2) FSR1H
408h(2) BSR
409h(2) WREG
40Ah(1, 2) PCLATH
40Bh(2) INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
BSR4
BSR3
BSR2
BSR1
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
40Ch
Unimplemented
40Dh
Unimplemented
40Eh
Unimplemented
40Fh
Unimplemented
410h
Unimplemented
411h
Unimplemented
412h
Unimplemented
413h
Unimplemented
414h
Unimplemented
415h
TMR4
Timer 4 Module Register
0000 0000 0000 0000
416h
PR4
Timer 4 Period Register
1111 1111 1111 1111
417h
T4CON
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
418h
Unimplemented
419h
Unimplemented
41Ah
Unimplemented
41Bh
Unimplemented
41Ch
TMR6
Timer 6 Module Register
0000 0000 0000 0000
41Dh
PR6
Timer 6 Period Register
1111 1111 1111 1111
41Eh
T6CON
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000
41Fh
Unimplemented
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2009 Microchip Technology Inc.
Preliminary
DS41364B-page 43

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