PIC16F676-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F676-I/ML

14-Pin, Flash-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16F630/676

TABLE 2-2: PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, Page

BOD

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx 20,63

81h

OPTION_REG RAPU INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 14,32

82h

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000 19

83h

STATUS

IRP(2)

RP1(2)

RP0

TO

PD

Z

DC

C

0001 1xxx 13

84h

FSR

Indirect data memory Address Pointer

xxxx xxxx 20

85h

TRISA

—

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 21

86h

—

Unimplemented

—

—

87h

TRISC

—

—

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111

—

88h

—

Unimplemented

—

—

89h

—

Unimplemented

—

—

8Ah PCLATH

—

—

—

Write buffer for upper 5 bits of program counter

---0 0000 19

8Bh INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF 0000 0000 15

8Ch PIE1

EEIE

ADIE

—

—

CMIE

—

—

TMR1IE 00-- 0--0 16

8Dh

—

Unimplemented

—

—

8Eh PCON

—

—

—

—

—

—

POR

BOD

---- --qq

18

8Fh

—

—

90h

OSCCAL

91h

ANSEL(3)

CAL5

ANS7

CAL4

ANS6

CAL3

ANS5

CAL2

ANS4

CAL1

ANS3

CAL0

ANS2

—

ANS1

—

1000 00-- 18

ANS0 1111 1111 48

92h

—

Unimplemented

—

—

93h

—

Unimplemented

—

—

94h

—

Unimplemented

—

—

95h

WPUA

—

—

WPUA5 WPUA4

—

WPUA2 WPUA1 WPUA0 --11 -111

22

96h

IOCA

—

—

IOCA5

IOCA4

IOCA3

IOCA2

IOCA1

IOCA0 --00 0000

23

97h

—

Unimplemented

—

—

98h

—

Unimplemented

—

—

99h

VRCON

VREN

—

VRR

—

VR3

VR2

VR1

VR0

0-0- 0000

44

9Ah EEDAT

EEPROM data register

0000 0000 51

9Bh EEADR

—

EEPROM address register

0000 0000 51

9Ch EECON1

—

—

—

—

WRERR WREN

WR

RD

---- x000 52

9Dh EECON2

EEPROM control register 2 (not a physical register)

9Eh

ADRESL(3)

Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result

9Fh

ADCON1(3)

—

ADCS2 ADCS1 ADCS0

—

—

—

---- ---- 51

xxxx xxxx 46

—

-000 ---- 47,63

Legend:

Note 1:

2:

3:

– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.

IRP and RP1 bits are reserved, always maintain these bits clear.

PIC16F676 only.

DS40039F-page 12

 2010 Microchip Technology Inc.

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