PIC16F676-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F676-I/ML Datasheet PDF : 132 Pages
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PIC16F630/676
3.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC16F676 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-4:
Data Bus
DQ
WR
WPUA
CK Q
RD
WPUA
WR
PORTA
DQ
CK Q
WR
TRISA
DQ
CK Q
RD
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
Interrupt-on-Change
BLOCK DIAGRAM OF RA4
Analog
Input Mode CLK(1)
Modes
VDD
Weak
RAPU
Oscillator
Circuit
OSC1
CLKOUT
Enable
FOSC/4 1
0
CLKOUT
Enable
INTOSC/
RC/EC(2)
CLKOUT
Enable
Analog
Input Mode
VDD
I/O pin
VSS
QD
EN
QD
EN
To TMR1 T1G
To A/D Converter
RD PORTA
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3.2.3.6 RA5/T1CKI/OSC1/CLKIN
Figure 3-5 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 3-5:
BLOCK DIAGRAM OF RA5
Data Bus
DQ
WR
WPUA
CK Q
RD
WPUA
WR
PORTA
DQ
CK Q
WR
TRISA
DQ
CK Q
RD
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
Interrupt-on-Change
INTOSC
Mode
TMR1LPEN(1)
VDD
Weak
RAPU
Oscillator
Circuit
OSC2
VDD
INTOSC
Mode
I/O pin
VSS
(1)
QD
EN
QD
EN
RD PORTA
To TMR1 or CLKGEN
Note
1: Timer1 LP Oscillator enabled.
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
DS40039F-page 26
2010 Microchip Technology Inc.
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