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PIC16F688-E/SL View Datasheet(PDF) - Microchip Technology

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PIC16F688-E/SL Datasheet PDF : 202 Pages
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4.2.5.4 RA3/MCLR/VPP
Figure 4-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset with weak pull-up
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
MCLRE
VDD
Weak
Data Bus
Reset
RD
VSS
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
Interrupt-on-
change
MCLRE
MCLRE
QD
EN
QD
EN
RD PORTA
Input
pin
VSS
Q3
PIC16F688
4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• a Timer1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 4-5:
BLOCK DIAGRAM OF RA4
Data Bus
DQ
WR
WPUA
CK Q
Analog(3)
Input Mode CLK(1)
Modes
VDD
Weak
RD
WPUA
WR
PORTA
DQ
CK Q
WR
TRISA
DQ
CK Q
RD
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
RAPU
Oscillator
Circuit
OSC1
CLKOUT
Enable
Fosc/4 1
0
CLKOUT
Enable
INTOSC/
RC/EC(2)
CLKOUT
Enable
Analog(3)
Input Mode
VDD
I/O pin
VSS
QD
EN
Q3
QD
Interrupt-on-
change
To T1G
To A/D Converter
EN
RD PORTA
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: Analog Input mode is ANSEL.
© 2007 Microchip Technology Inc.
DS41203C-page 39

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