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PIC16F690T-ESS View Datasheet(PDF) - Microchip Technology

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PIC16F690T-ESS Datasheet PDF : 306 Pages
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PIC16F631/677/685/687/689/690
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
System
Clock
Output
Clock Monitor Output
(Q)
OSCFIF
Oscillator
Failure
Failure
Detected
Note:
Test
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2)
CPD
CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
OSCCON
IRCF2 IRCF1 IRCF0 OSTS HTS
LTS
SCS -110 x000 -110 x000
OSCTUNE
TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
Legend:
Note 1:
2:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 14-1) for operation of all register bits.
DS41262E-page 58
© 2008 Microchip Technology Inc.

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