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PIC16F72-04I/ML View Datasheet(PDF) - Microchip Technology

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PIC16F72-04I/ML Datasheet PDF : 136 Pages
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PIC16F72
FIGURE 14-16: A/D CONVERSION TIMING
BSF ADCON0, GO
134
(TOSC/2)(1)
131
Q4
130
A/D CLK 132
1 TCY
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
GO
DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
130 TAD A/D Clock Period
PIC16F72
1.6 — — μs TOSC based, VREF 3.0V
PIC16LF72
2.0 — — μs TOSC based,
2.0V VREF 5.5V
PIC16F72
2.0 4.0 6.0 μs A/D RC mode
PIC16LF72 3.0 6.0 9.0 μs A/D RC mode
131 TCNV Conversion Time (not including S/H time)
(Note 1)
9
9 TAD
132 TACQ Acquisition Time
5* — — μs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134 TGO Q4 to A/D Clock Start
— TOSC/2 —
— If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D
clock starts. This allows the
SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
© 2007 Microchip Technology Inc.
DS39597C-page 105

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