PIC16LF72-04I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LF72-04I/SS Datasheet PDF : 136 Pages
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PIC16F72
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
R/W-0 R/W-0 R/W-0
—
ADIF
—
—
SSPIF CCP1IF TMR2IF
bit 7
R/W-0
TMR1IF
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine.
The conditions that will set this bit are a transmission/reception has taken place.
0 = No SSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39597C-page 16
© 2007 Microchip Technology Inc.
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