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PIC16F72T-IP View Datasheet(PDF) - Microchip Technology

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PIC16F72T-IP Datasheet PDF : 136 Pages
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PIC16F72
5.9 Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
5.10 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 5-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh,8Bh, INTCON GIE PEIE TMR0IE
10Bh,18Bh
INTE
RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch
PIR1
— ADIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
— ADIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS39597C-page 32
© 2007 Microchip Technology Inc.

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