PIC16F/LF722A/723A
FIGURE 23-9:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR and VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if
PWRTE = 0 and VREGEN = 1.
2010 Microchip Technology Inc.
DS41417A-page 215