PIC16F76T-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F76T-I/SP Datasheet PDF : 174 Pages
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PIC16F7X
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100* THIGH Clock high time 100 kHz mode
4.0
— µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
— µs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
101* TLOW
Clock low time
100 kHz mode
4.7
— µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
— µs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
102* TR
SDA and SCL rise 100 kHz mode
—
1000
time
400 kHz mode 20 + 0.1CB 300
ns
ns CB is specified to be from
10 - 400 pF
103* TF
SDA and SCL fall 100 kHz mode
—
300
time
400 kHz mode 20 + 0.1CB 300
ns
ns CB is specified to be from
10 - 400 pF
90* TSU:STA START condition 100 kHz mode
4.7
— µs Only relevant for
setup time
400 kHz mode
0.6
—
µs Repeated START
condition
91* THD:STA START condition 100 kHz mode
4.0
— µs After this period the first
hold time
400 kHz mode
0.6
—
µs clock pulse is generated
106* THD:DAT Data input hold time 100 kHz mode
0
— ns
400 kHz mode
0
0.9 µs
107* TSU:DAT Data input setup 100 kHz mode
250
— ns (Note 2)
time
400 kHz mode
100
— ns
92* TSU:STO STOP condition 100 kHz mode
4.7
— µs
setup time
400 kHz mode
0.6
— µs
109* TAA
Output valid from 100 kHz mode
clock
400 kHz mode
—
3500 ns (Note 1)
—
— ns
110* TBUF
Bus free time
100 kHz mode
400 kHz mode
4.7
— µs Time the bus must be free
1.3
—
µs before a new transmission
can start
CB
Bus capacitive loading
—
400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
DS30325B-page 136
2002 Microchip Technology Inc.
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