PIC16F720-EML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F720-EML

20-Pin Flash Microcontrollers

Microchip Technology 

PIC16(L)F720/721

17.2.10 CLOCK SYNCHRONIZATION

When the CKP bit is cleared, the SCL output is held low

once it is sampled low. Therefore, the CKP bit will not

stretch the SCL line until an external I2C master device

has already asserted the SCL line low. The SCL output

will remain low until the CKP bit is set and all other

devices on the I2C bus have released SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (Figure 17-14).

17.2.11 SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses of data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if SSP interrupt is enabled).

FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

CKP

WR

SSPCON

DX

Master device

asserts clock

Master device

de-asserts clock

DX-1

 2010-2013 Microchip Technology Inc.

DS41430D-page 155

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