PIC16F767T-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F767T-I/ML

28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC16F7X7

2.2.2.4 PIE1 Register

The PIE1 register contains the individual enable bits for

the peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)

R/W-0

PSPIE(1)

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0 R/W-0 R/W-0

CCP1IE TMR2IE TMR1IE

bit 7

bit 0

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.

bit 6

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5

RCIE: AUSART Receive Interrupt Enable bit

1 = Enables the AUSART receive interrupt

0 = Disables the AUSART receive interrupt

bit 4

TXIE: AUSART Transmit Interrupt Enable bit

1 = Enables the AUSART transmit interrupt

0 = Disables the AUSART transmit interrupt

bit 3

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30498C-page 24

 2004 Microchip Technology Inc.

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