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PIC16F767T-I/ML View Datasheet(PDF) - Microchip Technology

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PIC16F767T-I/ML Datasheet PDF : 276 Pages
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PIC16F7X7
TABLE 4-4: CLOCK SWITCHING MODES
Current
System
Clock
SCS bits<1:0>
Modified to:
Delay
OSTS IOFS T1RUN
bit bit
bit
New
System
Clock
Comments
LP, XT, HS,
10
8 Clocks of 0
1(1)
T1OSC,
(INTRC)
INTRC
EC, RC FOSC<2:0> = LP,
XT or HS
0
INTRC The internal RC oscillator
or
frequency is dependant upon
INTOSC the IRCF bits.
or
INTOSC
Postscaler
LP, XT, HS,
01
8 Clocks of 0 N/A
1
INTRC,
(T1OSC)
T1OSC
EC, RC FOSC<2:0> = LP,
XT or HS
T1OSC T1OSCEN bit must be enabled.
INTRC
00
8 Clocks of 1 N/A
0
EC
T1OSC FOSC<2:0> = EC
EC
or
or
or
RC
FOSC<2:0> = RC
RC
INTRC
00
1024 Clocks 1 N/A
T1OSC FOSC<2:0> = LP,
+
XT, HS
8 Clocks of
LP, XT, HS
0 LP, XT, HS During the 1024 clocks,
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
LP, XT, HS
00
1024 Clocks 1 N/A
(Due to Reset)
LP, XT, HS
0 LP, XT, HS When a Reset occurs, there is
no clock transition sequence.
Instruction
execution and/or peripheral
operation is suspended unless
Two-Speed Start-up mode is
enabled, after which the INTRC
will act as the system clock
until the Oscillator Start-up
Timer has expired.
Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)
after the clock change.
2004 Microchip Technology Inc.
DS30498C-page 47

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