PIC16F753-I/SLQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F753-I/SLQTP Datasheet PDF : 238 Pages
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PIC16F753/HV753
When the phase delay count value is zero, phase
delay is disabled and the phase delay counter output
is true, thereby allowing the event signal to pass
straight through to complementary output driver flop.
11.7.1 CUMULATIVE UNCERTAINTY
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the
phase delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or
phase delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage.
EQUATION 11-1: PHASE, DEAD-BAND
AND BLANKING TIME
CALCULATION
Tmin = Count
F COG_clock
Tmax
=
--C----o---u---n---t---+-----1--
FCOG_clock
Tuncertainty = Tmax – Tmin
Also:
Tuncertainty
=
------------1-------------
FCOG_clock
Where:
T
Rising Phase Delay
Falling Phase Delay
Rising Dead Band
Falling Dead Band
Rising Event Blanking
Falling Event Blanking
Count
COGxPHR
COGxPHF
COGxDBR
COGxDBF
COGxBLKR
COGxBLKF
EQUATION 11-2: TIMER UNCERTAINTY
Given:
Count = Ah = 10d
FCOG_Clock = 8MHz
Therefore:
Tuncertainty
=
------------1-------------
FCOG_clock
= 8----M---1--H-----z- = 125ns
Proof:
Tmin
=
------C----o---u----n---t-----
FCOG_clock
= 125ns 10d = 1.25s
Tmax
=
-C----o---u----n---t---+-----1--
FCOG_clock
= 125ns 10d + 1
= 1.375s
Therefore:
Tuncertainty = Tmax – Tmin
= 1.375s – 1.25s
= 125ns
DS40001709A-page 96
Preliminary
2013 Microchip Technology Inc.
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