PIC16F87T/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F87T/ML

18/20/28-Pin Enhanced Flash MCUs with nanoWatt Technology

Microchip Technology 

PIC16F87/88

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bit for the EEPROM

write operation interrupt.

.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit, or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

REGISTER 2-7:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)

R/W-0

R/W-0

U-0

R/W-0

U-0

U-0

U-0

U-0

OSFIF

CMIF

—

EEIF

—

—

—

—

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3-0

OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)

0 = System clock operating

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

Unimplemented: Read as ‘0’

EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002-2013 Microchip Technology Inc.

DS30487D-page 23

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