PIC16C712T-04/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C712T-04/SO
Microchip Technology
PIC16C712T-04/SO Datasheet PDF : 108 Pages
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FIGURE 9-8:
VDD
33k
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
Q1
10k
MCLR
40k PIC16C7XX
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where
Vz = Zener voltage.
2: Internal Brown-out Reset circuitry
should be disabled when using this cir-
cuit.
FIGURE 9-9:
VDD
R1
R2
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
Q1
MCLR
40k PIC16C7XX
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
R1
VDD x
= 0.7 V
R1 + R2
2: Internal brown-out reset should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
PIC16C712/716
FIGURE 9-10: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
VDD
MCP809
Vss
VDD
RST
bypass
capacitor
VDD
MCLR
PIC16C7XX
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open
collector outputs with both high and low active
reset pins. There are 7 different trip point
selections to accommodate 5V and 3V systems
9.8 Time-out Sequence
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-11,
Figure 9-12, and Figure 9-13 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-13). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operat-
ing in parallel.
Table 9-5 shows the reset conditions for some special
function registers, while Table 9-6 shows the reset con-
ditions for all the registers.
9.9 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON has two
bits.
Bit0 is Brown-out Reset Status bit, BOR. If the BODEN
configuration bit is set, BOR is ’1’ on Power-on Reset.
If the BODEN configuration bit is clear, BOR is
unknown on Power-on Reset.
The BOR status bit is a "don't care" and is not neces-
sarily predictable if the brown-out circuit is disabled (the
BODEN configuration bit is clear). BOR must then be
set by the user and checked on subsequent resets to
see if it is clear, indicating a brown-out has occurred.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
© 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 57
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