PIC16C712T-04/SO View Datasheet(PDF) - Microchip Technology
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Description
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PIC16C712T-04/SO
Microchip Technology
PIC16C712T-04/SO Datasheet PDF : 108 Pages
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PIC16C712/716
9.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.13 for details on SLEEP mode.
9.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
9.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
9.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0, it must also be defined at 0xA0 in bank
1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the interrupt service routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS41106A-page 62
Preliminary
© 1999 Microchip Technology Inc.
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