PIC16C716T-04I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C716T-04I/SO

8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM

Microchip Technology 

PIC16C712/716

9.12 Watchdog Timer (WDT)

The Watchdog Timer is as a free running, on-chip, RC

oscillator which does not require any external compo-

nents. This RC oscillator is separate from the RC oscil-

lator of the OSC1/CLKIN pin. That means that the WDT

will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device have been stopped,

for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the STATUS register

will be cleared upon a Watchdog Timer time-out.

The WDT can be permanently disabled by clearing

configuration bit WDTE (Section 9.1).

WDT time-out period values may be found in the Elec-

trical Specifications section under TWDT (parameter

#31). Values for the WDT prescaler (actually a

postscaler, but shared with the Timer0 prescaler) may

be assigned using the OPTION_REG register.

Note:

The CLRWDT and SLEEP instructions clear

the WDT and the postscaler, if assigned to

the WDT, and prevent it from timing out and

generating a device RESET condition.

.

Note:

When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

prescaler assignment is not changed.

FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 4-2)

WDT Timer

0

1

M

U

X

Postscaler

8

WDT

Enable Bit

PSA

8 - to - 1 MUX

PS2:PS0

To TMR0 (Figure 4-2)

0

1

MUX

PSA

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

WDT

Time-out

FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name

Bits 13:8 Bit 7

Bit 6 Bit 5 Bit 4 Bit 3

Bit 2 Bit 1 Bit 0

2007h Config. bits

(1)

— BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0

81h

OPTION_REG

N/A

RBPU INTEDG T0CS T0SE PSA

PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 9-1 for operation of these bits.

© 1999 Microchip Technology Inc.

Preliminary

DS41106A-page 63

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