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PIC16C716T-04I/SO View Datasheet(PDF) - Microchip Technology

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PIC16C716T-04I/SO Datasheet PDF : 108 Pages
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PIC16C712/716
FIGURE 12-8: A/D CONVERSION TIMING
BSF ADCON0, GO
134
Q4
A/D CLK 132
A/D DATA
ADRES
ADIF
GO
SAMPLE
(TOSC/2) (1)
1 Tcy
131
130
7
6
5
4
3
2
1
0
OLD_DATA
NEW_DATA
SAMPLING STOPPED
DONE
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
TABLE 12-8 A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
130 TAD A/D clock period
Standard
Extended (LC)
Standard
Extended (LC)
131 TCNV Conversion time (not including S/H time)
(Note 1)
132 TACQ Acquisition time
Min
1.6
2.0
2.0
3.0
11
Note 2
Typ†
4.0
6.0
20
Max Units
Conditions
µs TOSC based, VREF 3.0V
µs TOSC based, VREF full range
6.0
µs A/D RC Mode
9.0
µs A/D RC Mode
11
TAD
µs
5*
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start
— TOSC/2 § —
— If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 TSWC Switching from convert sample time 1.5 §
TAD
: * These parameters are characterized but not tested.
: † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
: § This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 for min conditions.
© 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 89

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