PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 13-7: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK 132
A/D DATA
ADRES
ADIF
GO
SAMPLE
(TOSC/2) (1)
1 Tcy
131
130
7
6
5
4
3
2
1
0
OLD_DATA
NEW_DATA
SAMPLING STOPPED
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 13-8: A/D CONVERSION REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
130
TAD A/D clock period
1.6
2.0
—
µs VREF ≥ 3.0V
—
µs VREF full range
130
TAD A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
3.0
6.0
9.0
µs PIC16LC715, VDD = 3.0V
2.0
4.0
6.0
µs PIC16C715
131
TCNV Conversion time
—
(not including S/H
time). Note 1
9.5TAD
—
—
132
TACQ Acquisition time
Note 2
20
—
µs
*
†
Note 1:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
ADRES register may be read on the following TCY cycle.
DS30272A-page 124
© 1997 Microchip Technology Inc.