PIC16C715-10ESP View Datasheet(PDF) - Microchip Technology
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PIC16C715-10ESP Datasheet PDF : 176 Pages
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5.0 I/O PORTS
Applicable Devices 710 71 711 715
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is a 5-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers) which can configure
these pins as output or input.
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1: INITIALIZING PORTA
BCF
CLRF
BSF
MOVLW
MOVWF
STATUS, RP0
PORTA
STATUS, RP0
0xCF
TRISA
;
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<4> as outputs
; TRISA<7:5> are always
; read as '0'.
PIC16C71X
FIGURE 5-1: BLOCK DIAGRAM OF
RA3:RA0 PINS
Data
bus
WR
Port
D
Q
CK Q
Data Latch
D
Q
VDD
P
N
I/O pin(1)
WR
TRIS
CK Q
TRIS Latch
VSS
Analog
input
mode
RD TRIS
Q
D
TTL
input
buffer
EN
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 5-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data
bus
WR
PORT
DQ
CK Q
Data Latch
N
I/O pin(1)
WR
TRIS
DQ
CK Q
TRIS Latch
VSS
Schmitt
Trigger
input
buffer
RD TRIS
Q
D
RD PORT
ENEN
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
© 1997 Microchip Technology Inc.
DS30272A-page 25
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