PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F1513T-I/SS Datasheet PDF : 360 Pages
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PIC16(L)F1512/3
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full Detect bit, BF
of the SSPSTAT register, and the interrupt flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the SSPBUF
register to complete successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various Status conditions.
FIGURE 20-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010 SDO
Serial Input Buffer
(BUF)
SPI Slave SSPM<3:0> = 010x
SDI
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
SDI
SCK
Serial Clock
SDO
SCK
Shift Register
(SSPSR)
MSb
LSb
Slave Select
General I/O
SS
Processor 1
(optional)
Processor 2
DS40001624C-page 180
2012-2014 Microchip Technology Inc.
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