PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology
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PIC16F1513T-I/SS Datasheet PDF : 360 Pages
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PIC16(L)F1512/3
20.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins
counting. This ensures that the SCL high time will
always be at least one BRG rollover count in the event
that the clock is held low by an external device
(Figure 20-25).
FIGURE 20-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
BRG
Value
BRG
Reload
DX
DX ‚ – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
20.6.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not Idle.
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPCON2
is disabled until the Start condition is
complete.
2012-2014 Microchip Technology Inc.
DS40001624C-page 207
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