PIC16(L)F1512/3
FIGURE 25-12: A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
Q4
A/D CLK
A/D Data
(TOSC/2(1))
AD131
AD130
1 TCY
7
6
5
4
3
2
1
0
ADRESx
OLD_DATA
NEW_DATA
ADIF
1 TCY
GO
Sample AD132
Sampling Stopped
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 25-13: A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
A/D CLK
A/D Data
(TOSC/2 + TCY(1))
AD131
AD130
1 TCY
7
6
54
3
2
1
0
ADRESx
ADIF
GO
Sample AD132
OLD_DATA
Sampling Stopped
NEW_DATA
1 TCY
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 25-14: LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
LD001
LDO Regulation Voltage
— 3.4
—
V
LD002
*
†
LDO External Capacitor
0.1 —
1 F
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2012-2014 Microchip Technology Inc.
DS40001624C-page 303