PIC16LF1512-I/SP View Datasheet(PDF) - Microchip Technology
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PIC16LF1512-I/SP Datasheet PDF : 360 Pages
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PIC16(L)F1512/3
7.6.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
OSFIF
—
—
—
BCLIF
—
—
bit 7
R/W-0/0
CCP2IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-4
bit 3
bit 2-1
bit 0
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
2012-2014 Microchip Technology Inc.
DS40001624C-page 73
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