PIC16LF1902-I/P View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1902-I/P

28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

Microchip Technology 

10.2 Flash Program Memory Overview

It is important to understand the Flash program memory

structure for erase and programming operations. Flash

program memory is arranged in rows. A row consists of

a fixed number of 14-bit program memory words. A row

is the minimum size that can be erased by user software.

Flash program memory may only be written or erased

if the destination address is in a segment of memory

that is not write-protected, as defined in bits WRT<1:0>

of Configuration Word 2.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the PMDATH:PMDATL register pair.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

Then, new data and retained data can be

written into the write latches to reprogram

the row of Flash program memory.

See Table 10-1 for Erase Row size and the number of

write latches for Flash program memory.

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Device

PIC16LF1902/3

Row Erase

(words)

32

Write Latches

(words)

32

PIC16LF1902/3

10.2.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF PMCON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the PMDATH:PMDATL register pair; therefore, it can

be read as two bytes in the following instructions.

PMDATH:PMDATL register pair will hold this value until

another read or until it is written to by the user.

Note:

The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

10.2.2

FLASH MEMORY UNLOCK

SEQUENCE

The unlock sequence is a mechanism that protects the

Flash program memory from unintended self-write pro-

gramming or erasing. The sequence must be executed

and completed without interruption to successfully

complete:

• Row Erase

• Load program memory write latches

• Write of program memory write latches to pro-

gram memory

• Write of program memory write latches to User

IDs

The unlock sequence consist of the following steps:

1. Write 55h to PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOP instruction

5. NOP instruction

Once the WR bit is set, the processor will always force

two NOP instructions. If an Erase Row or Program Row

operation is being performed, the processor will stall

internal operations (typical 2 ms), until the operation is

complete and then resume with the next instruction. If the

operation was loading the program memory write latches,

the processor will always force the two NOP instructions

and continue uninterrupted with the next instruction.

Since the unlock sequence cannot be interrupted, global

interrupts should be disabled prior to the unlock sequence

and re-enabled after the unlock sequence is completed.

 2011 Microchip Technology Inc.

Preliminary

DS41455A-page 81

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