PIC18LC858T-I/L View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
PIC18LC858T-I/L Datasheet PDF : 366 Pages
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PIC18CXX8
15.4.3 MASTER MODE
15.4.4 I2C MASTER MODE SUPPORT
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START condition
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
Note:
The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
FIGURE 15-10: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
SDA
SDA In
Read
Internal
Data Bus
Write
SSPBUF
MSb
SSPSR
Shift
Clock
LSb
SSPM3:SSPM0
SSPADD<6:0>
Baud
Rate
Generator
START bit, STOP bit,
Acknowledge
Generate
SCL
SCL In
Bus Collision
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Note: I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 151
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