PIC18CXX8
REGISTER 17-11: TXERRCNT – TRANSMIT ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3 TEC2
bit 7
R-0
TEC1
R-0
TEC0
bit 0
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus off state occurs. When the bus has 128 occurrences of 11 con-
secutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 193