PIC18LF1320-I/PSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF1320-I/PSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger will:

Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.

Special Event Trigger

Set Flag bit CCP1IF

RB3/CCP1/P1A pin

TRISB<3>

Output Enable

QS

R

Output

Logic

CCP1CON<3:0>

Mode Select

Match

CCPR1H CCPR1L

Comparator

T3CCP1

01

TMR1H TMR1L

TMR3H TMR3L

TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

PIR1

—

ADIF

RCIF

TXIF

—

CCP1IF TMR2IF TMR1IF -000 -000 -000 -000

PIE1

—

ADIE

RCIE

TXIE

—

CCP1IE TMR2IE TMR1IE -000 -000 -000 -000

IPR1

—

ADIP

RCIP

TXIP

—

CCP1IP TMR2IP TMR1IP -111 -111 -111 -111

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

T1CON

RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

CCPR1L Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

T3CON

RD16

— T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu

ADCON0 VCFG1 VCFG0

—

CHS2

CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.

DS39605F-page 118

© 2007 Microchip Technology Inc.

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