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PIC18LF1320T-I/SOSQTP View Datasheet(PDF) - Microchip Technology

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PIC18LF1320T-I/SOSQTP Datasheet PDF : 308 Pages
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PIC18F1220/1320
FIGURE 22-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RB1/AN5/TX/
CK/INT1 pin
RB4/AN6/RX/
DT/KBI0 pin
125
126
Note: Refer to Figure 22-5 for load conditions.
TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Max
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK(DT hold time)
126 TckL2dtl Data Hold after CK(DT hold time)
10
15
Units
ns
ns
Conditions
TABLE 22-13: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL)
PIC18LF1220/1320 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
A01 NR
Resolution
10
bit ΔVREF 3.0V
A03 EIL
Integral Linearity Error
<±1
LSb ΔVREF 3.0V
A04 EDL Differential Linearity Error
<±1
LSb ΔVREF 3.0V
A06 EOFF Offset Error
<±1
LSb ΔVREF 3.0V
A07 EGN
A10 —
Gain Error
Monotonicity
<±1
guaranteed(2)
LSb ΔVREF 3.0V
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)
3
— AVDD – AVSS V For 10-bit resolution
A21 VREFH Reference Voltage High
AVSS + 3.0V — AVDD + 0.3V V For 10-bit resolution
A22 VREFL Reference Voltage Low
AVSS – 0.3V — AVDD – 3.0V V For 10-bit resolution
A25 VAIN Analog Input Voltage
VREFL
VREFH
V
A28 AVDD Analog Supply Voltage
VDD – 0.3
VDD + 0.3 V
A29 AVSS Analog Supply Voltage
VSS – 0.3
VSS + 0.3 V
A30 ZAIN Recommended Impedance of
2.5
kΩ
Analog Voltage Source
A40 IAD
A/D Conversion PIC18F1X20
180
μA Average current
Current (VDD) PIC18LF1X20
90
μA consumption when
A/D is on (Note 1)
A50 IREF VREF Input Current (Note 3)
±5
μA During VAIN acquisition.
±150
μA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
specification includes any such leakage from the A/D module.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
DS39605F-page 264
© 2007 Microchip Technology Inc.

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