PIC18LF1320T-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF1320T-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

WRITE_WORD_TO_HREGS

MOVF POSTINC0, W

MOVWF TABLAT

TBLWT+*

DECFSZ COUNTER

GOTO WRITE_WORD_TO_HREGS

PROGRAM_MEMORY

BCF

INTCON, GIE

MOVLW 55h

MOVWF EECON2

MOVLW AAh

MOVWF EECON2

BSF

EECON1, WR

NOP

BSF

INTCON, GIE

DECFSZ COUNTER_HI

GOTO PROGRAM_LOOP

BCF

EECON1, WREN

; get low byte of buffer data and increment FSR0

; present data to table latch

; short write

; to internal TBLWT holding register, increment

TBLPTR

; loop until buffers are full

; disable interrupts

; required sequence

; write 55H

; write AAH

; start program (CPU stall)

; re-enable interrupts

; loop until done

; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset, or a

WDT Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

6.6 Flash Program Operation During

Code Protection

See Section 19.0 “Special Features of the CPU” for

details on code protection of Flash program memory.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

TBLPTRU —

—

bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000 0000 0000

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000 0000 0000

TABLAT Program Memory Table Latch

0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE

RBIE TMR0IF INTF

RBIF 0000 000x 0000 000u

EECON2 EEPROM Control Register 2 (not a physical register)

—

—

EECON1 EEPGD CFGS

—

FREE WRERR WREN

WR

RD xx-0 x000 uu-0 u000

IPR2

OSCFIP

—

—

EEIP

—

LVDIP TMR3IP

—

1--1 -11- 1--1 -11-

PIR2

OSCFIF

—

—

EEIF

—

LVDIF TMR3IF

—

0--0 -00- 0--0 -00-

PIE2

OSCFIE

—

—

EEIE

—

LVDIE TMR3IE

—

0--0 -00- 0--0 -00-

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

© 2007 Microchip Technology Inc.

DS39605F-page 65

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