PIC18LF1320T-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF1320T-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Priority registers (IPR1, IPR2). Using the

priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

REGISTER 9-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

U-0

R/W-1 R/W-1 R/W-1

U-0

R/W-1

—

ADIP

RCIP

TXIP

—

CCP1IP

bit 7

R/W-1

TMR2IP

R/W-1

TMR1IP

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3

Unimplemented: Read as ‘0’

bit 2

CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39605F-page 82

© 2007 Microchip Technology Inc.

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