PIC18F4331-IP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F4331-IP

28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

Microchip Technology 

PIC18F2331/2431/4331/4431

TABLE 11-3: PORTB I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

I/O

Type

Description

RB0/PWM0

RB0

0

O

DIG LATB<0> data output; not affected by analog input.

1

I

TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input is enabled.

PWM0

0

O

DIG PWM Output 0.

RB1/PWM1

RB1

0

O

DIG LATB<1> data output; not affected by analog input.

1

I

TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input is enabled.

PWM1

0

O

DIG PWM Output 1.

RB2/PWM2

RB2

0

O

DIG LATB<2> data output; not affected by analog input.

1

I

TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input is enabled.

PWM2

0

O

DIG PWM Output 2.

RB3/PWM3

RB3

0

O

DIG LATB<3> data output; not affected by analog input.

1

I

TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input is enabled.

PWM3

0

O

DIG PWM Output 3.

RB4/KBI0/PWM5

RB4

0

O

DIG LATB<4> data output; not affected by analog input.

1

I

TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input is enabled.

KBI0

1

I

TTL Interrupt-on-change pin.

PWM5

0

O

DIG PWM Output 5.

RB5/KBI1/

PWM4/PGM

RB5

0

O

DIG LATB<5> data output.

1

I

TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1

1

PWM4(3)

0

PGM(2)

x

I

TTL Interrupt-on-change pin.

O

DIG PWM Output 4; takes priority over port data.

I

ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP

Configuration bit; all other pin functions are disabled.

RB6/KBI2/PGC

RB6

0

O

DIG LATB<6> data output.

1

I

TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.

KBI2

PGC

1

I

TTL Interrupt-on-change pin.

x

I

ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(1)

RB7/KBI3/PGD

RB7

0

O

DIG LATB<7> data output.

1

I

TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.

KBI3

PGD

1

I

TTL Interrupt-on-change pin.

x

O

DIG Serial execution data output for ICSP and ICD operation.(1)

x

I

ST Serial execution data input for ICSP and ICD operation.(1)

Legend:

Note 1:

2:

3:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

All other pin functions are disabled when ICSP or ICD is enabled.

Single-Supply Programming must be enabled.

RD5 is the alternate pin for PWM4.

 2010 Microchip Technology Inc.

DS39616D-page 117

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