PIC18LF4331T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF4331T-I/SO
Microchip Technology
PIC18LF4331T-I/SO Datasheet PDF : 392 Pages
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PIC18F2331/2431/4331/4431
14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>).
The interrupt is enabled by setting the TMR2 Match
Interrupt Enable bit, TMR2IE (PIE1<1>). A range of
16 postscale options (from 1:1 through 1:16 inclusive)
can be selected with the postscaler control bits,
T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
T2OUTPS<3:0>
2
T2CKPS<1:0>
FOSC/4
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
Reset
TMR2
8
14.3 Output of TMR2
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode. Timer2 can be optionally
used as the shift clock source for the SSP module
operating in SPI mode.
For additional information, see Section 19.0
“Synchronous Serial Port (SSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or SSP)
PR2
8
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
54
PIR1
—
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
57
PIE1
—
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
57
IPR1
—
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
57
TMR2 Timer2 Register
55
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
55
PR2
Timer2 Period Register
55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
2010 Microchip Technology Inc.
DS39616D-page 137
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