PIC18LF4331T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF4331T-I/SO

28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

Microchip Technology 

PIC18F2331/2431/4331/4431

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or two bits

of the TMR2 prescaler, the CCP1 pin is cleared. The

maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation:

EQUATION 16-3:

log

 FOSC 

FPWM

PWM Resolution (max) = log(2) bits

16.5.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP1 module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L

register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

5. Configure the CCP1 module for PWM operation.

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

10

10

10

8

7

6.58

TABLE 16-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values

on Page:

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

54

PIR1

—

ADIF

RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

57

PIE1

—

ADIE

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE

57

IPR1

—

ADIP

RCIP

TXIP SSPIP CCP1IP TMR2IP TMR1IP

57

TRISC

PORTC Data Direction Register

57

TMR2

Timer2 Register

55

PR2

Timer2 Period Register

55

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

55

CCPR1L Capture/Compare/PWM Register 1 Low Byte

56

CCPR1H Capture/Compare/PWM Register 1 High Byte

56

CCP1CON

—

—

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

56

CCPR2L Capture/Compare/PWM Register 2 Low Byte

56

CCPR2H Capture/Compare/PWM Register 2 High Byte

56

CCP2CON

—

—

DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0

56

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and

Timer2.

DS39616D-page 150

 2010 Microchip Technology Inc.

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