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PIC18LF4331T-IP View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC18LF4331T-IP Datasheet PDF : 392 Pages
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PIC18F2331/2431/4331/4431
BZ
Branch if Zero
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BZ n
-128 n 127
if Zero bit is ‘1’,
(PC) + 2 + 2n PC
None
1110 0000 nnnn nnnn
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to
PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero
=
PC
=
If Zero
=
PC
=
BZ Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
CALL
Subroutine Call
Syntax:
[ label ] CALL k [,s]
Operands:
0 k 1048575
s [0,1]
Operation:
(PC) + 4 TOS,
k PC<20:1>;
if s = 1:
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
1110 110s k7kkk kkkk0
1111 k19kkk kkkk kkkk8
Subroutine call of entire 2-Mbyte
memory range. First, the return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs. Then, the
20-bit value, ‘k’, is loaded into
PC<20:1>. CALL is a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
Read literal
‘k’<7:0>,
No
operation
Q3
Push PC to
Stack
No
operation
Q4
Read literal
‘k’<19:8>,
Write to PC
No
operation
Example:
HERE
CALL THERE,FAST
Before Instruction
PC
= address (HERE)
After Instruction
PC
=
TOS
=
WS
=
BSRS =
STATUSS =
address (THERE)
address (HERE + 4)
W
BSR
STATUS
DS39616D-page 298
2010 Microchip Technology Inc.

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