PIC18F4580T-E/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F4580T-E/SP
Microchip Technology
PIC18F4580T-E/SP Datasheet PDF : 484 Pages
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PIC18F2480/2580/4480/4580
FIGURE 27-13: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit 6 - - - - - -1
75, 76
SDI
MSb In
bit 6 - - - -1
74
Note: Refer to Figure 27-4 for load conditions.
LSb
LSb In
TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 —
of Byte 2
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time PIC18FXXXX
—
25
PIC18LFXXXX
45
76
TDOF
SDO Data Output Fall Time
—
25
78
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXXXX
PIC18LFXXXX
—
25
45
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDO Data Output Valid after PIC18FXXXX
TSCL2DOV SCK Edge
PIC18LFXXXX
—
50
100
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
—
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
DS39637A-page 442
Preliminary
2004 Microchip Technology Inc.
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