PIC18LF2685-ISP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF2685-ISP

28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2682/2685/4682/4685

9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Priority registers (IPR1, IPR2). Using the

priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP(1)

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

CCP1IP

R/W-1

TMR2IP

R/W-1

TMR1IP

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

1 = High priority

0 = Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2

CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.

DS39761B-page 124

Preliminary

© 2007 Microchip Technology Inc.

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