PIC18LF4682-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF4682-I/ML

28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2682/2685/4682/4685

17.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, setting the CKP bit will not assert the

SCL output low until the SCL output is already

sampled low. Therefore, the CKP bit will not assert the

SCL line until an external I2C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I2C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 17-12).

FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

DX

DX – 1

SCL

CKP

WR

SSPCON

Master device

asserts clock

Master device

deasserts clock

© 2007 Microchip Technology Inc.

Preliminary

DS39761B-page 207

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