PIC18LF4682-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF4682-I/ML

28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2682/2685/4682/4685

If the IRCF bits were previously at a non-zero value or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multiplexer while the primary clock is started. When the

primary clock becomes ready, a clock switch to the

primary clock occurs (see Figure 3-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. The IDLEN and SCS bits are not affected by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3:

TRANSITION TIMING TO RC_RUN MODE

Q1 Q2 Q3 Q4 Q1

INTRC

1

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

PC

2

3

n-1 n

Clock Transition

PC + 2

Q2 Q3 Q4 Q1 Q2 Q3

PC + 4

FIGURE 3-4:

TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

INTOSC

Multiplexer

OSC1

PLL Clock

Output

Q1

Q2

Q3

Q4

TOST(1)

TPLL(1)

CPU Clock

Peripheral

Clock

Program

Counter

PC

SCS1:SCS0 bits Changed

OSTS bit Set

Q1

Q2 Q3 Q4 Q1 Q2 Q3

1 2 n-1 n

Clock

Transition

PC + 2

PC + 4

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

DS39761B-page 36

Preliminary

© 2007 Microchip Technology Inc.

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