PIC18LF2685T-ISO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF2685T-ISO
Microchip Technology
PIC18LF2685T-ISO Datasheet PDF : 484 Pages
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PIC18F2682/2685/4682/4685
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Return from Interrupt
RETFIE {s}
s ∈ [0,1]
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
GIE/GIEH, PEIE/GIEL.
0000 0000 0001 000s
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
1
2
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
POP PC
from stack
Set GIEH or
GIEL
No
operation
Example:
RETFIE 1
After Interrupt
PC
=
W
=
BSR
=
STATUS
=
GIE/GIEH, PEIE/GIEL =
TOS
WS
BSRS
STATUSS
1
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Return Literal to W
RETLW k
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
0000 1100 kkkk kkkk
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
Q2
Read
literal ‘k’
No
operation
Q3
Process
Data
No
operation
Q4
POP PC
from stack,
Write to W
No
operation
Example:
CALL TABLE; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL; W = offset
RETLW k0; Begin table
RETLW k1;
:
:
RETLW kn; End of table
Before Instruction
W
=
After Instruction
W
=
07h
value of kn
DS39761B-page 394
Preliminary
© 2007 Microchip Technology Inc.
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