PIC18LF4550T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF4550T-I/SO
Microchip Technology
PIC18LF4550T-I/SO Datasheet PDF : 438 Pages
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PIC18F2455/2550/4455/4550
FIGURE 28-6:
OSC1
CLKO AND I/O TIMING
Q4
Q1
10
CLKO
13
14
I/O pin
(Input)
17
I/O pin
(Output)
Old Value
Note:
20, 21
Refer to Figure 28-4 for load conditions.
Q2
19
18
15
Q3
11
12
16
New Value
TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10 TosH2ckL OSC1 ↑ to CLKO ↓
—
75
200
ns (Note 1)
11
TosH2ckH OSC1 ↑ to CLKO ↑
—
75
200
ns (Note 1)
12 TckR
CLKO Rise Time
—
35
100
ns (Note 1)
13 TckF
CLKO Fall Time
—
35
100
ns (Note 1)
14 TckL2ioV CLKO ↓ to Port Out Valid
—
— 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO ↑
0.25 TCY + 25 —
—
ns (Note 1)
16 TckH2ioI Port In Hold after CLKO ↑
0
—
—
ns (Note 1)
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX
100
—
—
ns
18A
Port Input Invalid
PIC18LFXXXX
200
—
—
ns VDD = 2.0V
(I/O in hold time)
19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup
time)
0
—
—
ns
20 TioR
Port Output Rise Time PIC18FXXXX
—
10
25
ns
20A
PIC18LFXXXX
—
—
60
ns VDD = 2.0V
21 TioF
Port Output Fall Time PIC18FXXXX
—
10
25
ns
21A
PIC18LFXXXX
—
—
60
ns VDD = 2.0V
22† TINP
INTx pin High or Low Time
TCY
—
—
ns
23† TRBP
RB7:RB4 Change INTx High or Low Time
TCY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
© 2009 Microchip Technology Inc.
DS39632E-page 389
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