PIC18F2455T-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F2455T-I/ML
Microchip Technology
PIC18F2455T-I/ML Datasheet PDF : 438 Pages
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PIC18F2455/2550/4455/4550
FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
78
79
79
78
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
74
73
Note: Refer to Figure 28-4 for load conditions.
LSb In
TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
3 TCY
—
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
—
73A Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 —
of Byte 2
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
35
—
75
TdoR
SDO Data Output Rise Time PIC18FXXXX
—
25
PIC18LFXXXX
—
45
76
TdoF
SDO Data Output Fall Time
—
25
78
TscR
SCK Output Rise Time
PIC18FXXXX
—
25
(Master mode)
PIC18LFXXXX
—
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after PIC18FXXXX
TscL2doV SCK Edge
PIC18LFXXXX
—
50
—
100
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
© 2009 Microchip Technology Inc.
DS39632E-page 393
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