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PIC18F2455T-I/ML View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC18F2455T-I/ML Datasheet PDF : 438 Pages
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PIC18F2455/2550/4455/4550
FIGURE 28-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT/SDO
pin
121
121
120
122
Note: Refer to Figure 28-4 for load conditions.
TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXXXX
40
PIC18LFXXXX —
100
121 Tckrf
Clock Out Rise Time and Fall Time PIC18FXXXX
20
(Master mode)
PIC18LFXXXX —
50
122 Tdtrf
Data Out Rise Time and Fall Time PIC18FXXXX
20
PIC18LFXXXX —
50
Units Conditions
ns
ns VDD = 2.0V
ns
ns VDD = 2.0V
ns
ns VDD = 2.0V
FIGURE 28-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT/SDO
pin
125
126
Note: Refer to Figure 28-4 for load conditions.
TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Max
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK (DT hold time)
126 TCKL2DTL Data Hold after CK (DT hold time)
10
15
Units
ns
ns
Conditions
© 2009 Microchip Technology Inc.
DS39632E-page 401

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